1. Field of the Invention
The present invention is related to a phase selector, and more particularly, to a phase selector capable of tolerating jitter and suitable for a clock and data recovery circuit.
2. Description of the Prior Art
Generally, in a serial interface, a transmitter end combines data with a clock signal into an input data stream, and outputs the input data stream to a receiver end. This way, a clock and data recovery circuit is required at the receiver end, for restoring information of the clock signal from the input data stream, and sampling the input data stream according to a phase of the obtained clock signal, so as to attain the actual data transmitted by the input data stream.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are diagrams illustrating a clock and data recovery circuit 100 of the prior art. As shown in FIG. 1, the clock and data recovery circuit 100 comprises an over-sampling circuit 110, a phase detecting module 120, a phase selector 130 and a back-end processing module 140. The over-sampling circuit 110 over-samples an input data stream DSIN, for generating an over-sampling signal SOS. The phase detecting module 120 comprises a transition detecting circuit 121 and a phase detecting circuit 122. The transition detecting circuit 121 detects a transition of the over-sampling signal SOS, for generating a transition signal STR. The phase detecting circuit 122 generates a phase detecting signal SPD according to the transition signal STR. The phase selector 130 generates a phase selecting signal SPH according to the phase detecting signal SPD. The back-end processing module 140 selects the appropriate over-sampling signal SOS to be an output data signal SDOUT.
More specifically, assume the over-sampling circuit 110 over-samples the input data stream DSIN with quintupled frequency as shown in FIG. 2, so in each cycle (e.g. cycle T1-T3), the over-sampling circuit 110 over-samples the input data stream DSIN at over-sampling instances P0-P4, for obtaining the over-sampling signal SOS. Intervals in between the over-sampling instances P0-P4 can be defined as regions R0-R4. Practically, the transition detecting circuit 121 can be realized with an XOR circuit. Therefore, when the over-sampling signal SOS transforms from logic “0” to logic “1” or from logic “1” to logic “0”, the transition detecting circuit 121 generates the transition signal STR of logic “1” accordingly. In other words, when the transition signal STR is logic “1”, the input data stream DSIN undergoes transition at a region corresponding to the transition signal STR. The phase detecting circuit 122 obtains the region corresponding to when the transition of the input data stream DSI occurs, by detecting the transition signal STR of logic “1”. This way, the phase detecting circuit 122 can output the phase detecting signal SPD to represent the transition region of the input data stream DSIN. For instance, in the cycle T1 of FIG. 2, the input data stream DSIN generates a rising edge in the region R1, so the phase detecting circuit 122 outputs the phase detecting signal SPD representing the region “R1”; in the cycle T2, the input data stream DSIN generates a falling edge in the region R1, so the phase detecting circuit 122 outputs the phase detecting signal SPD representing the region “R1”; in the cycle T3, the input data stream DSIN generates a rising edge in the region R0, so the phase detecting circuit 122 outputs the phase detecting signal SPD representing the region “R0”. The phase selector 130 can obtain the transition region of the input data stream DSIN in each cycle according to the transition signal STR (e.g. the transition region is R1 in the cycle T1). The phase selector 130 can accumulate accumulated transition numbers NR0-NR4 in each cycle according to the transition region in each cycle, and the phase selector 130 generates the phase selecting signal SPH according to the largest accumulated transition number.
For instance, the transition region in the cycle T1 is R1, so in the cycle T1, the accumulated transition number NR1 of the phase selector 130 is 1, and the other accumulated transition numbers are 0. The accumulated transition number NR1 possesses the largest value for the time being, so the phase selector 130 generates the phase selecting signal SPH representing the region “R1”. The transition region in the cycle T2 is also R1, so in the cycle T2, the accumulated transition number NR1 of the phase selector 130 is accumulated to be 2, and the other accumulated transition numbers are 0. The accumulated transition number NR1 still possesses the largest value for the time being, so the phase selector 130 still generates the phase selecting signal SPH representing the region “R1”. The transition region in the cycle T3 is R0, so in the cycle T3, the accumulated transition number NR1 of the phase selector 130 is still 2, the accumulated transition number NR0 of the phase selector 130 becomes 1, and the other accumulated transition numbers remain 0. Although the transition region in the cycle T3 is R0, since the accumulated transition number NR1 still possesses the largest value, the phase selector 130 still generates the phase selecting signal SPH representing the region “R1”.
The back-end processing module 140 can determine the region in which the transition of the clock signal occurs according to the phase selecting signal SPH. Hence the back-end processing module 140 can select an appropriate over-sampling signal SOS to be the output data signal SDOUT. For instance, in the cycle T1, the back-end processing module 140 can determine the over-sampling instance P4 to correspond to a steady state of the input data stream DSIN (i.e. since the over-sampling instance P4 is approximately in the middle between the region R1 in the cycle T1 and the region R1 in the cycle T2), according to the transition region R1. This way, the back-end processing module 140 selects the over-sampling signal SOS corresponding to the over-sampling instance P4 to be the output data signal SDOUT.
However, for the phase selector 130 of the prior art, assuming initial transitions of the clock signal of the transmitter end all occur in the region R1, the accumulated transition number NR1 corresponding to the region R1 has accumulated to a degree that the accumulated transition number NR1 far exceeds the accumulated transition numbers NR0 and NR2 which correspond to regions R0 and R2, respectively. At this moment, if the input data stream DSIN has a small jitter (e.g. the region corresponding to a transition edge of the clock signal of the transmitter end changes from region R1 to R0), since a value of the accumulated transition number NR1 is still far greater than the accumulated transition numbers NR0 and NR2 (in other words, the memory effect of the phase selector 130 of the prior art), the clock and data recovery circuit 100 still outputs the phase selecting signal SPH representing the region “R1”. Therefore, the back-end processing module 140 is likely to select the incorrect over-sampling signal SOS to be the output data signal SDOUT.
Furthermore, assuming values of the accumulated transition numbers NR0 and NR1 are approximately the same, if the input data stream DSIN has a large jitter (e.g. the region corresponding to a transition edge of the clock signal of the transmitter end switches continuously between regions R0 and R1), since the largest accumulated transition number switches continuously between accumulated transition numbers NR0 and NR1, the clock and data recovery circuit 100 continuously selects the over-sampling signal SOS corresponding to different over-sampling instances (such as over-sampling instances P3 and P4) to be the output data signal SDOUT. Consequently, system instability results, causing inconvenience to the user.